Basler raL2048-48gm User Manual Page 55

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AW00118302000 Camera Functional Description
Basler racer GigE 45
6 Camera Functional
Description
This chapter provides an overview of the camera’s functionality from a system perspective. The
overview will aid your understanding when you read the more detailed information included in the
later chapters of the user’s manual.
Each camera employs a single line CMOS sensor chip designed for monochrome imaging. For 2k
cameras, the sensor includes 2048 pixels with a pixel size of 7 µm x 7 µm. For 4k/6k cameras, the
sensor consists of two/three 2k sensor segments with a pixel size of 7 µm x 7 µm, resulting in a total
of 4096/6144 pixels. For 8k/12k cameras, the sensor consists of 2/3 4k sensor segments with a
pixel size of 3.5 µm x 3.5 µm, resulting in a total of 8192/12288 pixels. See Fig. 11 on page 46 for
an overview of the different sensor architectures.
Acquisition start, frame start, and line start can be controlled via externally generated hardware
trigger signals. These signals facilitate periodic or non-periodic frame/line start. Modes are available
that allow the length of exposure time to be directly controlled by the external line start signal or to
be set for a pre-programmed period of time.
Acquisition start, frame start, and exposure time can also be controlled by parameters transmitted
to the camera via the Basler pylon API and the GigE interface.
Accumulated charges are read out of the sensor when exposure ends. At readout, accumulated
charges are moved from the sensor’s light-sensitive elements (pixels) into the analog processing
section of the sensor (Fig. 11 on page 46). As the charges move from the pixels to the analog
processing section, they are converted to voltages proportional to the size of each charge. The
voltages from the analog processing section are next passed to a bank of 12 Bit Analog-to-Digital
converters (ADCs).
Finally, the gray values pass through a section of the sensor where they receive additional digital
processing and then they are moved out of the sensor. As each gray value leaves the sensor, it
passes through an FPGA and into an image buffer (Fig. 12 on page 47). All shifting is clocked
according to the camera’s internal data rate. Shifting continues until all image data has been read
out of the sensor.
The gray values leave the image buffer and pass back through the FPGA to an Ethernet controller
where they are assembled into data packets. The packets are then transmitted via an Ethernet
network to a network adapter in the host PC. The Ethernet controller also handles transmission and
receipt of control data such as changes to the camera’s parameters.
The image buffer between the sensor and the Ethernet controller allows data to be read out of the
sensor at a rate that is independent of the data transmission rate between the camera and the host
computer. This ensures that the data transmission rate has no influence on image quality.
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